These teachings relate generally to leakage current reduction, and, more particularly, to leakage current reduction in asynchronous circuits.
Reducing power consumption has become very important in recent years due to increases in transistor density and clock frequency as well as consumer trends in high-performance, portable, and embedded applications. Dynamic power losses are significant, but can be mitigated by techniques such as clock gating, which reduces the power consumption of idle sections of synchronous circuits. Asynchronous designs offer this advantage inherently, as they are data driven and are only active while performing useful work. In other words, asynchronous circuits implement the equivalent of a fine-grained clock gating network. However, while dynamic power losses have been dominant in the past, static power loss has become a major contributor to power consumption in nanoscale technologies due to leakage currents:                Source-to-Drain (Isd) leakage, also known as subthreshold leakage, has increased due to recent reductions in threshold voltages.        Gate-to-Channel (Ig) leakage manifests as bidirectional electron tunneling between the substrate and gate through the gate oxide, which has increased due to shrinking gate oxide thickness.        Source/Drain-to-Substrate (Iinv) leakage currents are another name for the reverse-bias currents between a transistor's active regions and bulk.        
There are a wide array of techniques designed to reduce leakage currents. The most effective techniques involve power gating circuits, essentially cutting the pull-up network (PUN) and pull-down network (PDN) off from one or both power rails during idle or “sleep” periods. During active periods, the circuit is reconnected to the power rails in a process known as “wake up” or power up. While power gating has been adapted for use in asynchronous circuits most of these efforts involve direct application of synchronous techniques to asynchronous systems. As such, the unique capabilities of asynchronous circuits have not been fully leveraged in the context of power gating. Many asynchronous circuit families are robust to a wide range of supply voltages, ambient temperatures, and process variations.
There is a need for power gating techniques that utilize the unique capabilities of asynchronous circuits.